Basics in Electronics

1.Purpose of Tank circuit.
      To amplify a selective range of frequency this circuit is used.Output impedence(Rc) is replaced by tank circuit

Operation:When initially C is charged,it finds path to discharge through L it stores the energy in form of magnetic field.Now according to lenz law,magnetic field start collapsing and this in turn charges the capacitor in opposite direction.After some time capacitor fully charges.Here magnetic energy is converted back to eletrostatic energy.Now the capacitor again starts discharging through inductor L .This capacitor produces alternating current in tank circuit.

By selecting the L and C and placing it in f=1/(2pi root(LC)),We can fix the frequency and at a specified frequency we can amplify the signals.

2.Why in P-type semiconductor majority charge carries are holes and in N-type semiconductor majority charge carries are electrons

Semiconductors like silicon and germanium belong to 4th group of periodic table.To form a P-type semiconductor silicon(4 valence electrons)  is doped with 3rd group elements like berillium(3 valence electrons) so one electron is short.so in P-type majority charge carries are holes(positive charge).In the same manner

To form N-type semiconductor silicon(4 valence electrons) is doped with 5th group elements like phosphorus(5 valence electrons) so one electron is more.so in N-type majority charge carries are electrons(negative charge)

3.why cant capacitor stores only DC but not AC

AC signal is which varies accordingly with time, and has amplitude in both positive and negative levels like a sine wave.Capacitor also does charging for the positive cycle of AC and discharges for negative cycle of AC so net is zero. 

4.Transistors disadvantages

a.Input impedence : Rb for the transistor is low.Actually the input impedence of CC configuration is around 500kohms which is sufficient.But since we place R1,R2 for biasing purpose(to place the transistor to act as an amplifier)the net impedence decreases(R2//R1//Ri).To overcome this situation we have 2 techniques they are Darlington connection and Bootstrap emitter follower.But since we cant adopt this type of situations we consider this as a disadvantage because a week signal should not drive the transistor.

b.Stability:This is also one of the reason to implement the FET(field effect transistor).We desire a fixed operating point that to in active region with Ib,Ic,Vce. The flow of I2 into BJT results in dissipation of electrical energy in form of heat . That results in rise of temperature which in turn increases Ic0 but Ic depends upon Ic0. so Ic also increases and operating point is disturbed, it is referred as Bias Instability.

5.Why in BJT conduction is from Emitter to Collector and not viceversa.

First off all one should remember that BJT is not a symmetrical device (Emitter and Collector regions are not interchangable).As we know BJT provides two configurations i.e NPN and PNP.In any of these  Base(middle region) is lightly doped to have small recombination ,Emitter is heavily doped  and collector is moderately doped.So normally when base current is applied,conduction is carried from higher region to a lower region(process known as Diffusion) since emitter is heavily doped and collector is moderately doped,conduction is from Emitter to Collector.This is reason behind why in  BJT conduction is from Emitter to Collector and not viceversa.

6.Why P mos is ON for logic 0 , OFF for logic 1 and N mos is ON for logic 1,OFF for logic 0

When Vgs is positive there is force of attraction between gate(positive) terminal and N majority charge carriers electrons(negative) so no channel is formed between two highly doped N regions.By this we can say that P mos will be in OFF state when logic 1(high) is applied.

When Vgs is 0 or negative due to force of repulsion between gate(negative)and N majority carriers electrons(negative) and channel formation takes place which leads to conduction from source to drain.So P mos conducts when logic 0 is applied.

Similar action is followed in N mos

 When Vgs is positive there is force of repulsion between gate(positive) terminal and P majority charge carriers holes(positive) so  channel is formed between two highly doped P regions.By this we can say that N mos will be in ON state when logic 1(high) is applied.

When Vgs is 0 or negative due to force of attraction between gate(negative)and P majority carriers holes(positive) and no channel formation takes place between two highly doped P regions.So N mos doesn't conducts when logic 0 is applied.

7.Why P mos connected in pull up network where as N mos connected in pull down network

or

source of P mos is connected to Vdd and source of N mos connected to Vss

As i said before P mos will be in ON state when logic 0 is applied i.e Vgs is negative this happens when gate terminal is negative and source is positive,So in P mos source is always connected to Vdd which is positive.Coming to N mos it will be in ON  state when logic 1 is applied i.e Vgs is positive this happens when gate terminal is positive and source is negative,So in N mos source is always connected to Vss which is negative.This is reason why P mos is connected in pull up network and N mos is connected in pull down network.